For a recent semiconductor device, a Fin-FET (Field Effect Transistor) has been proposed as a new transistor structure to attain power saving and speed-up. The Fin-FET includes a substrate portion and a fin portion formed by pattering a semiconductor substrate (for example, Si substrate). A gate electrode is formed on the side and upper surfaces of the fin portion, thereby forming a channel in the fin portion.
When the transistor structure is changed from a conventional planar FET to the Fin-FET, the device performance can be improved. On the other hand, the semiconductor manufacturing process becomes complex because the structure changes from a 2D structure to a 3D structure. In addition, as the wiring pattern size decreases, the manufacturing process becomes more complex.
In the Fin-FET, especially, burying an STI (Shallow Trench Isolation) becomes more difficult along with the pattern size reduction. In the conventional CVD, for example, when the trench width of the STI is 70 to 100 nm or less, a gap is formed in the STI, and complete burying is impossible.
There has been devised a method of burying PSZ (polysilazane) having excellent burying properties as an STI using an application method. PSZ is a polymer with a basic structure —SiH2—NH— and is converted into silicon dioxide (SiO2) upon annealing in a steam atmosphere.
At this time, when the steam temperature is high, PSZ attains characteristics similar to those of SiO2. Simultaneously, however, the side walls of the fin portion made of Si oxidize. On the other hand, when the steam temperature is low, conversion of PSZ to SiO2 is weaker although oxidation of the side walls of the fin portion is suppressed. In this case, SiO2 converted from PSZ is etched faster by an etchant. That is, since the etching rate of SiO2 converted from PSZ is higher than that of the SiO2 film liner formed on the surface of the fin portion, steps are formed in the STI structure.
As described above, in the conventional method of burying the STI using PSZ, it is difficult to obtain a desired STI shape. For this reason, a problem arises even in, for example, the process of manufacturing a punch-through stopper later, resulting in degradation of the device characteristics of the Fin-FET.